Programmable row selection in liquid crystal display drivers

ABSTRACT

Liquid crystal display device ( 100 ) comprising an LCD display screen ( 102 ), column driver means ( 105 ), and row driver means ( 106 ) with N row slices ( 63.1, 42.1 ), whereby N is the number of row electrodes ( 2 ) of the LCD display screen ( 102 ). Furthermore, the device ( 100 ) comprises an input ( 44 ) for receiving a set of p orthogonal functions. This input ( 44 ) is connected to the column driver means ( 105 ) and the row driver means ( 106 ). Each row slice ( 63.1, 42.1 ) comprises a function selector ( 63   .n ) selecting an orthogonal function from the set of p orthogonal functions, and a time-division multiplex decoder ( 40   .n ) for transmitting row selection information to the row electrodes ( 2 ) depending on a clock signal applied to an input.

The present invention relates to improved drivers for use in liquidcrystal displays (LCDs). In particular, the present invention relatesthe free programmability of the row selection function in displaydrivers for LCDs.

Today's LCD displays comprise row and column drivers. These driverstypically include a memory unit (e.g., a random access memory (RAM)).The content to be displayed on the LCD screen is shifted into thismemory. It is then fetched from the memory using an appropriateaddressing scheme and applied to the respective rows and/or columns ofthe LCD screen.

A standard problem of LCD drivers is the selection of different rowswhere the data is output on the screen. Scrolling, for example, is anoperation that is very complex. Present drivers often only change theread address that is applied to the memory for fetching data from thememory. The order of the display row selection stays mostly unchanged oris very hard to change. Changing the order of the display row selectionwould require quite a number of multiplexers and wiring. The displayingof RAM data at different locations on the screen is very complex.Especially for multi-row addressing (MRA) this would require a verycomplex RAM access scheme.

An example of a conventional LCD display driving scheme is illustratedin FIGS. 1A and 1B. In FIG. 1A, a situation is depicted where thecontent of the RAM cells is fetched by applying appropriate readaddresses to the input on the left hand side of the RAM 10. The contentof the first RAM cell that is being addressable by applying the startaddress ‘0’, is applied to the uppermost row 12.1 of the LCD displayscreen 11. The content of the next RAM cell (address ‘1’) is applied tothe second row 12.2, and so forth. If the application program or theuser performs a scrolling function on the screen 11, the content of therows has to be vertically shifted upwards or downwards, depending on thedirection of scrolling. An example is shown in FIG. 1B. The content ofthe RAM cell 13.1 at the start address is displayed at the row 12.1, thecontent of the next RAM cell is displayed at the next row 12.1+1, an soon. The start address which defines the information being displayed atthe first row 12.1. on the LCD screen 11 is now addressing another RAMcell, namely RAM cell 13.1. In other words, in current implementations,the scrolling function is realized by changing the read address of theRAM 10.

The same principle is illustrated in FIGS. 2A and 2B, with the onlydifference, that a so-called MRA-scheme is used. In such an MRAimplementation, a plurality of LCD rows is addressed at once. Asillustrated in FIG. 2A, each RAM cell stores the content of four displayrows. By applying the start address ‘0’ to the MRA RAM 14, the contentfor the rows 12.1 through 12.4. is fetched from the RAM 14. Whenimplementing a scrolling function, as illustrated in FIG. 2B, alwaysfour rows are scrolled together. The content of the second RAM cell 15.2is shifted to the last four rows 12.n through 12.n+3 of the displayscreen 11. When a freely programmable scrolling is to be implementedusing an MRA RAM, a complex RAM addressing scheme or a scheme withmultiple RAM access cycles would be required. The scrolling isrestricted to a multiple of the number of simultaneously selected rows p(in FIGS. 2A and 2B, p=4).

With the increasing size of the displays the p value increases as well.This in turn decreases the degree of freedom for scrolling. A solutionwould be to read the RAM in a more complex way. This, however, wouldrequire a complex RAM addressing or multiple RAM accesses. The firstapproach blows up the address decoding by a significant amount. Thesecond approach makes memory necessary after the RAM.

The demand for a reduced power consumption leads to implementations withan adaptable p value, as the optimal p value varies for differentmultiplex rates.

There is an increasing demand for more freedom and flexibility ofaddressing the rows of an LCD display screen. This would allow tosupport such functions as scrolling, freely programmable multiplex rateswith freely programmable active areas on the display screen, severalactive areas on one display screen, mirroring in Y-direction,chip-on-glass (COG) or tape carrier packaging (TCP), and so forth.

It is an object of the present invention to provide a scheme thatovercomes the disadvantages of known approaches.

It is an object of the present invention to provide a scheme that allowsto write the content of an LCD driver memory to any display row desired.

It is an object of the present invention to provide a scheme that allowsa freely programmable selection of rows.

These and other objects are accomplished by a liquid crystal displaydevice comprising an LCD display screen, column driver means, and rowdriver means with a plurality of row slices. The display device furthercomprise an input for receiving a set of orthogonal functions, saidinput being connected to the column driver means and the row drivermeans. Each row slice comprises a function selector for selecting anorthogonal function from the set of orthogonal functions, and atime-division multiplex decoder for transmitting row selectioninformation to row electrodes of the LCD display screen, depending on aclock signal applied to an input of the time-division multiplex decoder.

According to the present invention the rows can be freely programmed inorder to write the RAM content to any display row desired. Thisinvention concerns a scheme that allows to write the content of an LCDdriver memory to any display row desired. Furthermore the inventivescheme allows to freely program the selection of rows.

Further advantageous implementations are claimed in claims 2-11.

For a more complete description of the present invention and for furtherobjects and advantages thereof, reference is made to the followingdescription, taken in conjunction with the accompanying drawings, inwhich:

FIG. 1A is a schematic representation of a conventional display deviceindicating the relationship between the cells of a RAM and the rows of adisplay screen;

FIG. 1B is a schematic representation indicating how scrolling by fourrows is realized in a conventional display device;

FIG. 2A is a schematic representation of a conventional MRA displaydevice indicating the relationship between the cells of a RAM and therows of a display screen;

FIG. 2B is a schematic representation indicating how scrolling by eightrows is realized in a conventional MRA display device;

FIG. 3 is a schematic block diagram of a conventional display device;

FIG. 4 is a schematic block diagram of part of a display device,according to the present invention;

FIG. 5 is a schematic representation indicating how scrolling isrealized in an MRA display device (with p=4), according to the presentinvention;

FIG. 6 is a schematic block diagram of part of a display device,according to the present invention;

FIG. 7 is a schematic representation indicating how scrolling isrealized in display device with four simultaneously selected rows,according to the present invention;

FIG. 8A is a schematic representation of an application example,according to the present invention;

FIG. 8B is a schematic representation of another application example,according to the present invention;

FIG. 9 is a schematic block diagram of a display device, according tothe present invention;

FIG. 10 is a schematic block diagram of part of a display device,according to the present invention.

Before addressing various embodiments of the present invention, a briefdescription of a typical liquid crystal display (LCD) device 1 is given.An LCD device 1, as illustrated in FIG. 3, typically comprises a firstsubstrate provided with row or selection electrodes 2 (shown ashorizontal lines) and a second substrate provided with column or dataelectrodes 3 (shown as vertical lines). The overlapping parts of the rowelectrodes 2 and column electrodes 3 define pixels 4. In addition, anLCD device 1 comprises drive means 5 for driving the column electrodes 3in conformity with an image to be displayed, and drive means 6 fordriving the row electrodes 2.

According to a first embodiment of the present invention, a statemachine 30 is employed, as illustrated in FIG. 4. This state machine 30is responsible for the sequence of the selection of the rows 2 of adisplay screen (note that the display screen as such is represented inFIG. 4 by a simple matrix of row electrodes 2 and column electrodes 3).There is a control logic 31 that in addition to the state machine 30comprises a RAM address generator 32, a time-division multiple (TDM)access controller 33 and a TDM encoder 34. The control logic 31 isconnected via a clock bus 35 and a selection bus 36 to the row drivermeans 37. A TDM scheme is employed to reduce the number of physical buslines. The data are applied via the selection bus 36 to the individualrow slice 39.1-39.n of the row driver means 37 and the clock signalbeing applied via the clock bus 35 decides which row slice actuallyhandles/processes the data. An address generated by the RAM addressgenerator 32 is applied via a connection 43 to a RAM 50 for retrieval ofdata. These data are then processed by column driver means 105 togetherwith a set of orthogonal functions F_(i){f₀ . . . f_(p−1)} before beingapplied to the column electrodes 3 of the display screen. The orthogonalfunctions are fed via an input 44 to the column driver means 105.

The RAM 50 (cf. FIG. 5) is divided into blocks of p rows, that arealways accessed as a whole (p is the number of simultaneously selectedrows in the MRA driving technique). That is, each RAM cell stores p dataentries. In the present example, p=4 and the start address is 2 (cf.FIG. 5). Therefore only one address for every MRA block of p rows isneeded. This makes the RAM decoding much easier and the RAM 50 smaller.To have fill flexibility, the data of a RAM block can be output to anydesired p display rows (see FIG. 5 for an example). The rows of thedisplay screen 51 do not have to be adjacent. This is done by the statemachine 30 being part of the control logic 31, that can be cut to fitthe needs of each chip. The control logic 31 generates a set of p rowaddresses at an output 38. The row addresses are then encoded anddistributed to the row slices 39.1-39.n using a TDM scheme for encoding.Each row slice 39.1-39.n has a TDM decoder 40.n for decoding the TDMsignals received, a level shifter 41.n that holds the selection signalfor one time slot as only p rows are selected in one time slot. Theoutput signal at the output of the TDM decoders is either 0V or V_(dd).The level shifters 41.n shift the potential so that it either assumes 0Vor V_(lcd). The level shifters 41.n are connected to the respective rowoutput pads 42.n and the row electrodes 2 of the display screen. Notethat p can be any number, i.e., p=1, 2, 3, . . . . The level shifters41.n and many of the other components are standard components well knownin the art.

As illustrated in FIG. 5, with the present invention one can define ascrolling area 52 within the display screen 51. It is possible to freelyscroll the rows inside this scrolling area 52. Note that for sake ofsimplicity the RAM 50 is directly connected to the rows of the displayscreen 51. In reality, there is no such direct connection since there isat least the column driver means 105 situated between the RAM 50 and thedisplay screen. FIG. 5 shows the logic relationship between RAM cellsand the respective rows of the display screen 51.

According to one embodiment, the following driving scheme can be used.The basic idea is to start reading the RAM 50 always at the address ‘0’and to change the selection of the row dependent on certain programmedsettings. When p=8, eight different orthogonal functions F_(i)={f₀ . . .f_(p−1)} may be employed. These orthogonal functions F_(i) are appliedto the rows slices of the display screen 51. The selection of the outputsignals that are applied to the row pads 42.n depend on these orthogonalfunctions F_(i). Each row of the display screen 51 has a correspondingselection signal that tells when the respective row has to be driven ata voltage V_(lcd) or V_(ss). All other rows when not being selected aredriven at a voltage V_(c). Note that V_(c)=V_(lcd)/2, where V_(lcd) isthe supply voltage of the display screen. The selection of the outputsignals applied to the row pads 42.n depends on the following threesignals (further details are given in connection with FIG. 10):

-   -   the orthogonal function F_(i) (the one function applied to this        particular row) switches between V_(lcd) and V_(ss);    -   a selection row signal (row_sel) switches between the selected        signal of the orthogonal function F_(i) and V_(c);    -   a tristate signal for break before make and for testing        (rc_tristate): all switches are open. The rows and columns are        multiplexed in blocks and shortened on a tester board. Therefore        those row pads 42.n that are not selected must be tristate.

It is thus possible to generate any desired output pattern. Theinterface between the state machine 30 and the row slices 39.n staysalways the same. This allows for an improved re-usability resulting in ashortened time-to-market for LCD products implementing the presentinvention.

Another embodiment is described in connection with FIGS. 6 and 7. Thisembodiment is based on an MRA driving technique which asks for a directcorrespondence of a function applied to the column electrodes of thedisplay screen and a function applied to the row electrodes, where thatdata should be displayed. Therefore to have full flexibility one must beable to select which of the p row functions is output at a particularrow. A system 60 (cf FIG. 6) is proposed that calculates the selectionof the appropriate function out of the number of the function used byits neighbor's output stage. The interconnection between the digitalpart of the display device and the function selectors 63.n is restrictedto an initial value I0 and the information where to start with function0 (see FIG. 6). The distribution of the orthogonal functions F_(i) iscircular, hence an add-one-circuit 61 can be used in each functionselector 63.n to follow this circulation. The add-one-circuit 61 has anoverride which forces its output to be zero. The function F is used toadapt the count value to the structure of the RAM, where necessary. Theoutputs 62.1, 62.2, and 62.3 of the function selectors 63.1, 63.2, and63.3 are connected to the row electrode pads of the display screen (notillustrated in FIG. 6).

Two examples according to the present invention are described below.These two examples are given assuming that a system 60 is employed thatuses 8 orthogonal functions F_(i). It is only a three bit total, so itrolls over at 7 to 0. The first example is illustrated in FIG. 8A. Theinitial value I0=5. The add-one-circuit 61 of the first row slice 63.1add +1 to the initial value. The result (I0+1=6) is given at the bottomof the first box 71.1. This step is repeated in the row slice 63.2 and 7is obtained as result. The roll over takes place at 7, as mentionedabove. This means that the next row slice 63.3 outputs a 0 as result. Asillustrated in FIG. 8A, certain intermediate rows are disabled. Theserows are shown with a grey background. The row slice 71.x+1 after theone corresponding to the one representing the last intermediate row 71.xstarts at 0 again, since the function 0 is applied to itsadd-one-circuit 61. As schematically illustrated on the right hand sideof FIG. 8A, the fact that certain intermediate rows are disabled allowsto skip a corresponding area 73 on the display screen 72.

A second example is given in FIG. 8B. In this example there are twoareas of row slices 81 and 82 that have been disabled. These two areas81, 82 correspond to two row blocks 91 and 92 on the screen 90. All rowsof these two blocks 91 and 92 are unused in this example. The function 0defines the first active row slice 83.1 corresponding to the first row84.1. The add-one-circuit 61 step-by-step adds one to the value until 7is reached. At the row slice 83.8, the roll over occurs. The next rowslice 83.9 start with a value of 0 again.

Another embodiment of a system 100 in accordance with the presentinvention is shown in FIG. 9. The system 100 comprise row driver means106 and column driver means 105. Data are taken from a RAM 50 andtransferred to the column driver 105 via a bus 103. In order to be ableto illuminate the desired pixels 4 of the display screen 102, a setF_(i) of orthogonal functions f₀ . . . f_(p−1) is applied to the rowdriver means 106 and the column driver means 105 via a line 44. Asschematically indicated in FIG. 9, the row driver means 106 comprises anarray of p row slices each having at least one function selector 63.nand a row pad 42.n. The function selector 63.n can be similar to the onedescribed in connection with FIG. 6.

Part of another embodiment is illustrated in FIG. 10. This Figureillustrates the relationship between the voltages V_(lcd) and V_(ss),the selection row signal (row_sel), and the tristate signal(rc_tristate). The TDM decoder performs a selection of rows depending onthe clock signal being applied via a clock bus 35, and the functionselector 63.1 provides for a selection of one function out of the setF_(i) of orthogonal functions f₀ . . . f_(p−1). The tristate signal(rc_tistate) is applied for break before make and for testing. The levelshifter provides an output signals to transmission gate switches 45.1.The transmission gate switches 45.1 are controlled by the output signalsof the level shifter 41.1. At the output of the switches 45.1, one ofthe following voltages is being made available: V_(lcd) or V_(ss) orV_(c).

In the drawings and specification there has been set forth preferredembodiments of the invention and, although specific terms are used, thedescription thus given uses terminology in a generic and descriptivesense only and not for purposes of limitation.

1. Liquid crystal display device comprising an LCD display screen,column driver means, row driver means having N row slices, whereby N isthe number of row electrodes of the LCD display screen, an input forreceiving a set of p orthogonal functions, said input being connected tothe column driver means and the row driver means, whereby each row slicecomprises a function selector selecting an orthogonal function from theset of p orthogonal functions, a time-division multiplex decoder fortransmitting row selection information to the row electrodes dependingon a clock signal applied to an input of the time-division multiplexdecoder.
 2. The device of claim 1, further comprising a control logic.3. The device of claim 2, wherein the control logic comprises a statemachine serving as row selection generator for the selection of p rowsout of the N rows, and a RAM address generator.
 4. The device of claim3, wherein the control logic comprises a time-division multiple accesscontroller and a time-division multiple access encoder.
 5. The device ofclaim 4, wherein the control logic is connected via a clock bus and aselection bus to the row driver means.
 6. The device of claim 1, furthercomprising a RAM being divided into blocks of p rows.
 7. The device ofclaim 1 being enabled to define a scrolling area within the displayscreen.
 8. The device of claim 1, wherein an driving technique isemployed.
 9. The device of claim 8, wherein the selection of outputsignals being applied to the row electrodes depends on the orthogonalfunction selected from the set of p orthogonal functions.
 10. The deviceof claim 1, wherein the function selectors of the row slices areinterconnected so as to be able to calculate the selection of anappropriate orthogonal function out of the number of the orthogonalfunction used by a preceding function selector.
 11. The device of claim2 being enabled to define that certain intermediate rows are disabledwithin the display screen.